Conventional CMOS circuitry utilizes the single gate for all logical function implementation. As the circuit scales up, valuable real estate on the chip is consumed due to additional circuitry needed for the logic functions. For example, in a tri-state buffer, ENABLE and ENABLEN circuitry (including ENABLE and ENABLEN signal lines and respective FETS) are required for each buffer. (See, for example, FIG. 2.) Accordingly, as the amount of tri-state buffers increase on the chip, e.g., n+1, the ENABLE and ENABLEN circuitry also increases by the same amount, n+1. In essence, as each of the tri-state buffers include an additional FET for each ENABLE signal, the increase in chip area usage becomes very large over time.